There are conventional power semiconductor devices using SIC substrates, such as Schottky diodes, pn diodes, MOSFETs, etc. Such power semiconductor devices introduce various types of termination structures in order to prevent the concentration of an electric field at the pn junction. Such of termination structures include the JTE (Junction Termination Edge) structure (see Non-Patent Document 1, for example).
Characteristically, the JTE structure can be formed easily by ion implantation. Also, the JTE structure is easy to design, by setting the carrier concentration of the JTE layer such that the JTE layer is completely depleted at the time of dielectric breakdown.
Also, there are techniques for reducing the electric-field strength at the JTE surface by covering the pn junction and JTE with a third layer (Patent Document 1,for example).
Non-Patent Document 1: B. Jayant Baliga, “POWER SEMICONDUCTOR DEVICES”, pp. 111-113.
Patent Document 1: Japanese Patent Application Laid-Open No. 2002-507325